W7500

Product Description

The IOP4IoT W7500 chip is the one-chip solution which integrates an ARM Cortex-M0 (including 128kB Flash) and the hardwired TCP/IP core for various embedded application platforms, especially for Internet of Things applications. The TCP/IP core is a market-proven hardwired TCP/IP stack (WIZnet W5500) with an integrated Ethernet MAC. The stack supports multiple protocols, including TCP, UDP, ICMP, ARP, IGMP and PPoE. The expertise of more than 15 years of product development has been incorporated into this product.

Features

• ARM Cortex-M0
  • 48MHz maximum frequency
• Hardwired TCP/IP Core8 Sockets
  
  • SRAM for socket: 32 KB
  • MII (Medium-Independent Interface)
• PHYI
  • C+ IP101G
• Memory
  • Flash: 128 KB
  • Large flexible-size SRAM buffer for various User Application
    • Min 16KB available if full 32KB socket buffer used
    • Max 48KB available if no socket buffer used
  • ROM for boot code: 6 KB
• Clock, reset and supply management
  • POR (Power-On Reset)
  • Internal Voltage Regulator : 3.3V to 1.5V
  • 8-to-24MHz external crystal oscillator
  • Internal 8MHz RC Oscillator
  • PLL for CPU clock
• ADC : 12bit, 8ch, 1Msps
• DMA
  • 6-channel DMA controller
  • Peripheral supported: UARTs, SPIs
• GPIO
• 53 I/Os (16 IO x 3ea, 5 IO x 1ea)
• Debug mode
  • Serial Wire Debug (SWD)
• Timer/PWM
  • 1 Watchdog (32-bit down-counter)
  • 4 Timers (32-bit or 16-bit down-counter)
  • 8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
• Communication Interfaces
  • 3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
  • 2 SPI
  • 2 I2C (Master/Slave, Fast-mode (400 kbps))
• Crypto
  • 1 RNG (Random Number Generator): 32-bit random number
• Package64 TQFP (7x7 mm)
   

Related Links

WIZnet Documentation

W7500 product page on wiznet.io