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Quick Overview

latest 4-in-1 chip Including ARM Cortex-M0 + Hardwired TCP/IP based on W5500 + MAC + PHY embedded in a 64LQFP package.


Product Description

The IOP4IoT W7500 chip is the one-chip solution which integrates an ARM Cortex-M0 (including 128kB Flash) and the hardwired TCP/IP core for various embedded application platforms, especially for Internet of Things applications. The TCP/IP core is a market-proven hardwired TCP/IP stack (WIZnet W5500) with an integrated Ethernet MAC. The stack supports multiple protocols, including TCP, UDP, ICMP, ARP, IGMP and PPoE. The expertise of more than 15 years of product development has been incorporated into this product.

A 4-digit datecode is printed on every chip identifying the week of production. Datecodes greater than 1720 (year 2017, week 20) mean the chip already is Rev. 3 which has improved stability. In case you have any questions please feel free to contact us.


  • ARM Cortex-M0
    • 48 MHz maximum frequency
  • Hardwired TCP/IP Core
    • 8 Sockets
    • SRAM for socket: 32 kB
  • PHY
    • IC+ IP101G
  • Memory
    • Flash: 128 KB
    • Large flexible-size SRAM buffer for various user applications
      • Min 16 kB available if full 32 kB socket buffer used
      • Max 48 kB available if no socket buffer used
    • ROM for boot code: 6 kB
  • Clock, reset and supply management
    • POR (Power-On Reset)
    • Internal Voltage Regulator : 3.3V to 1.5V
    • 8 to 24 MHz external crystal oscillator
    • Internal 8 MHz RC Oscillator
    • PLL for CPU clock
  • ADC : 12 bit, 8 ch, 1 Msps
  • DMA
    • 6-channel DMA controller
    • Peripheral supported: UARTs, SPIs
  • GPIO
    • 34 I/Os (15 IO x 2 ea, 4 IO x 1 ea)
  • Debug mode
      • Serial Wire Debug (SWD)
  • Timer/PWM
    • 1 Watchdog (32 bit down-counter)
    • 4 Timers (32 bit or 16 bit down-counter)
    • 8 PWMs (32 bit counter/timers with programmable 6 bit prescaler)
  • Communication Interfaces
    • 3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
    • 2 SPI
    • 2 I2C (Master/Slave, Fast-mode (400 kbps))
  • Crypto
    • 1 RNG (Random Number Generator): 32-bit random number
  • Package
    • 64 LQFP (7x7 mm)


Related Links

W7500p official documentation in the WIZnet Wiki

More references for W7500p in the WIZnetMuseumLogo WIZnetMuseum

Additional Information

Dimension 7 x 7 mm
Ethernet I/F PHY
Operating Temperature TBA
Operating Voltage No
Functions No
Auto Negotiation No
Network sockets count 8
internal DPRAM buffer memory 32 kB
Package No
pin count No
auto MDIX No
Wake on Lan Yes
Power Down Mode Yes
typ. Power Consumption TBA
MCU core ARM Cortex-M0
Core speed 48 MHz
RAM 48 kB
ROM 128 kB
Boot ROM 6 kB
Interrupt controller No
I/O ports 34 I/Os
Timer / Counter 1 Watchdog, 4 Timer, 8 PWM
SPI (max. speed) 80 MHz
PHY chip internal
pin pitch No
Ethernet Speed No
UART (max speed) No
parallel memory bus No
Debug I/F SWD
Manufacturer No

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