€3.99 €3.35
Delivery Time
5 - 7 d
In stock
3 in 1 chip for the Internet connectivity Hardwired TCP/IP + MAC + PHY High Speed SPI Interface

Hardware TCP/IP Performance and Ease of Use to Low-Cost ‘IoT’ Applications

Product Description

The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface). W5500 suits users in need of stable internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE..


  • 48LQFP lead-free package (7x7mm, 0.5mm pitch)
  • Hardwired TCP/IP protocols: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
  • Unattackable hardware engine for preventing network attacks such as flooding, spoofing, injection
  • Host Interface: SPI (up to 80MHz, mode 0, 3)
  • 8 Independent hardware socket
  • Internal 32Kbytes memory for TCP/IP packet processing
  • 10BaseT / 100Base TX Auto Negotiable Ethernet PHY Embedded
  • 3.3V Operation with 5V I/O signal tolerance
  • LED outputs (full/half duplex, link speed, active)
  • Reduced heat dissipation (W5500: 40℃ / other chips : 60-70℃)
  • Efficient power operation: power down & wake-on LAN over UDP


Related Links

W5500 Data sheet

W5500 Application notes

W5500 Linux Driver

Minimal HTTP server with W5500

More references for W5500 in the WIZnetMuseumLogo WIZnetMuseum

More Information
Manufacturer WIZnet
Dimension 7 mm x 7 mm
Ethernet I/F PHY
Operating Temperature -40 °C to +85 °C
Operating Voltage 3.3 V
Functions 3-in-1, TCP/IP + MAC + PHY
Network sockets count 8
internal DPRAM buffer memory 32 kB
Package QFN
pin count chip 64
pin pitch 0.50 mm
Ethernet Speed 10/100
Protocol IPv4
Auto Negotiation Yes
Wake on Lan Yes
Power Down Mode Yes
MCU core ARM Cortex M0
Core speed 96 MHz
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