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W6100-Q
€2.86
€2.40
Delivery Time
5 - 7 d
3 in 1 chip for the Internet connectivity
Hardwired TCP/IP + MAC + PHY
Both SPI and parallel bus Interface 48QFN
Product Description
The W6100 is a Hardwired TCP/IP embedded Ethernet Controller that enables easier Internet Connection for embedded Systems using SPI (Serial Peripheral Interface) and Parallel Bus that incorporates IPv6 and is pincompatible to W5100S
W6100 suits users in need of stable Internet Connectivity Best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC, and PHY. The implemented Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE which has been proven through various Applications over many years. W6100 uses a 16 Kbytes Internal Buffer as its Data Communication Memory.
By using W6100, users can implement the Ethernet Application they need by using a simple socket Program instead of handling a complex Ethernet Controller. It is possible to use 8 independent hardware sockets simultaneously.
W6100 users can implement High-Speed Network Communication. In order to reduce the power consumption of the system, W6100 provides a Power Down mode and can be enabled by Wake On Lan.
Information for users of the W6100: The new W6100 and W5100S is not fully pin-to-pin compatible with the W5100, but the software compatibility is kept, hence the software for the W5100 can be used with the W6100/W5100S without any modification.
Features
- Supports hardwired TCP/IP protocols: TCP, UDP, IPv6, IPv4, ICMPv6, ICMPv4, IGMP, MLDv1, ARP, PPPoE
- Supports IPv4/IPv6 dual stack
- Supports 8 independent SOCKETs simultaneously with 32KB memory
- Supports SOCKET-less commands: ARP, ICMPv6 (ARP, DAD, NA, RS) command for IPv6 auto-configuration & network monitoring (PING, PING6)
- Supports Ethernet PHY power down mode & system clock switching for power save
- Supports wake on LAN over UDP
- Supports serial & parallel HOST interface: High speed SPI (MODE 0/3), system BUS with 2 address signal & 8bit data
- Internal 32Kbytes memory for TX/ RX Buffers
- 10BaseT/ 10BaseTe / 100BaseTX Ethernet PHY integrated
- Supports auto negotiation (full/half duplex, 10 and 100-based)
- Supports auto-MDIX only on auto-negotiation mode
- Does not support IP fragmentation & jumbo packet
- 3V operation with 5V I/O signal tolerance
- Network indicator LEDs (full/half duplex, link, 10/100 speed, active)
- 48 Pin LQFP & QFN lead-free package (7x7mm, 0.5mm pitch)
- PIN-2-PIN compatible with W5100S
Related Links
| Manufacturer | WIZnet |
|---|---|
| Dimension | 7 mm x 7 mm, 0.5 mm pitch |
| Ethernet I/F | PHY |
| Operating Temperature | -40 °C to +85 °C |
| Operating Voltage | 3.3 V |
| Functions | 3-in-1, TCP/IP + MAC + PHY |
| Network sockets count | 8 |
| internal DPRAM buffer memory | 32 kB |
| Package | QFN |
| pin count chip | 48 |
| MCU I/F | 8 bit (indirect) |
| pin pitch | 0.50 mm |
| Ethernet Speed | 10/100 |
| Protocol | IPv4, IPv6 |
| Auto Negotiation | Yes |
| Wake on Lan | Yes |
| Power Down Mode | Yes |
| MCU core | ARM Cortex M0 |
| Core speed | 96 MHz |