€2.50 €2.10
Delivery Time
5 - 7 d
3 in 1 chip for the Internet connectivity Hardwired TCP/IP + MAC + PHY Both SPI and parallel bus Interface 48LQFP

Product Description

Hardware TCP/IP Performance and Ease of Use to Low-Cost ‘IoT’ Applications

The W5100S is a Hardwired TCP/IP embedded Ethernet Controller that enables easier Internet Connection for embedded Systems using SPI (Serial Peripheral Interface) and Parallel Bus. 

W5100S suits users in need of stable Internet Connectivity Best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC, and PHY. The implemented Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE which has been proven through various Applications over many years. W5100S uses a 16 Kbytes Internal Buffer as its Data Communication Memory.

By using W5100S, users can implement the Ethernet Application they need by using a simple socket Program instead of handling a complex Ethernet Controller. It is possible to use 4 independent hardware sockets simultaneously. 

The W5100S SPI supports up to 70 MHz speed and the new efficient SPI Protocol, so users can implement High-Speed Network Communication. In order to reduce the power consumption of the system, W5100S provides a Power Down mode and can be enabled by Wake On Lan.

Information for users of the W5100: The new W5100S is not fully pin-to-pin compatible with the W5100, but the software compatibility is kept, hence the software for the W5100 can be used with the W5100S without any modification.



  • 48LQFP lead-free package (7x7mm, 0.5mm pitch)
  • Host Interface: SPI (up to 70MHz, mode 0, 3) and Parallel System Bus with 2 Address signals and 8 Bits Data
  • Unattackable hardware engine for preventing network attacks such as flooding, spoofing, injection
  • 4 Independent hardware sockets simultaneously 
  • supports various Internet Protocols: TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE
  • Internal 16 Kbytes memory for TCP/IP packet processing
  • socket-less commands possible: ARP request and ping requests
  • 10BaseT / 100Base TX Auto Negotiable Ethernet PHY Embedded
  • Auto-MDIX in auto-negotiation mode (Half/Full Duplex, 10/100 MBit/s speed)
  • IP fragmentation not supported, ARP-cache table will not be stored permanently
  • 3.3V operating voltage with 5V I/O signal tolerance
  • LED outputs (full/half duplex, link, 10/100 speed, active)
  • Reduced heat dissipation (W5500: 40℃ / other chips : 60-70℃)
  • Efficient power operation: power down & main clock gating as well as wake-on LAN over UDP

Related Links

WIZnet Documentation
W5100S-L product page on wiznet.io

More Information
Manufacturer WIZnet
Dimension 7 mm x 7 mm
Ethernet I/F PHY
Operating Temperature -40 °C to +85 °C
Operating Voltage 3.3 V
Functions 3-in-1, MCU + TCP/IP + MAC
Network sockets count 4
internal DPRAM buffer memory 16 kB
Package LQFP
pin count chip 48
MCU I/F 8 bit (indirect)
pin pitch 0.50 mm
Ethernet Speed 10/100
Protocol IPv4
Auto Negotiation Yes
Wake on Lan Yes
Power Down Mode Yes
MCU core ARM Cortex M0
Core speed 96 MHz
Write Your Own Review
You're reviewing:W5100S-L