W5500

Details

Hardware TCP/IP Performance and Ease of Use to Low-Cost ‘IoT’ Applications

Product Description

The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that enables easier internet connection for embedded systems using SPI (Serial Peripheral Interface). W5500 suits users in need of stable internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE..

Features

48LQFP lead-free package (7x7mm, 0.5mm pitch)
Hardwired TCP/IP protocols: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
Unattackable hardware engine for preventing network attacks such as flooding, spoofing, injection
Host Interface: SPI (up to 80MHz, mode 0, 3)
8 Independent hardware socket
Internal 32Kbytes memory for TCP/IP packet processing
10BaseT / 100Base TX Auto Negotiable Ethernet PHY Embedded
3.3V Operation with 5V I/O signal tolerance
LED outputs (full/half duplex, link speed, active)
Reduced heat dissipation (W5500: 40℃ / other chips : 60-70℃)
Efficient power operation: power down & wake-on LAN over UDP

Additional Information

Dimension	7 x 7 mm
Ethernet I/F	MDI (PHY)
Operating Temperature	-40°C to +85°C
Operating Voltage	3.3 V
Functions	3-in-1, TCP/IP+MAC+PHY
Auto Negotiation	Yes
Network sockets count	8
internal DPRAM buffer memory	32 kB
Package	QFN
pin count	64
auto MDIX	No
Wake on Lan	Yes
Power Down Mode	Yes
typ. Power Consumption	132 mA
SPI (max. speed)	85 MHz
MCU I/F	SPI
PHY chip	internal
pin pitch	0.50 mm
MII	No
Ethernet Speed	10/100
parallel memory bus	No
Manufacturer	WIZnet